1. Field of the Invention
The present invention relates generally to a semiconductor device and fabrication method thereof, and more particularly, to a stacked semiconductor structure and fabrication method thereof.
2. Description of Related Art
Given the trend toward multifunction, higher electrical performance and high-speed operation, more and more semiconductor devices integrated with a plurality of chips or packages are released.
With reference to FIG. 1, U.S. Pat. No. 5,222,014 proposes a stacked semiconductor package structure, which includes a first ball grid array (BGA) substrate 11 having pads 110 provided on an upper surface thereof, a semiconductor chip 10 mounted on the first BGA substrate 11, an encapsulant 13 encapsulating the semiconductor chip 10, and a second packaged BGA substrate 12 mounted and electrically connected to the pads 110 of the first BGA substrate 11 through solder balls 14.
However, in the above stacked semiconductor package structure, the number of the pads 110 for electrically connecting the second BGA substrate 12 and the first BGA substrate 11, types of packages to be stacked, and installation of electrical inputs/outputs (I/O) are subject to the size of the encapsulant 13. In other words, the types of the stacked packages and the number of the electrical I/O must be selected according to layout of the pads 110. Moreover, height of the encapsulant 13 provided on the first BGA substrate 11 should be minimized (generally limited to below 0.3 mm) to meet the limitation of height of the solder balls 14 during the stacking process, thereby increasing the difficulty of the process.
With reference to FIG. 2, U.S. Pat. No. 6,828,664 proposes another stacked semiconductor package structure, which includes a first BGA substrate 21 having pads 210 provided on an upper surface thereof, a semiconductor chip 20 mounted on the first BGA substrate 21 and electrically connected to the first BGA substrate 21 through bonding wires 25, a second BGA substrate 22 mounted and electrically connected to the pads 210 through solder balls 24, and an encapsulant 23 for encapsulating the semiconductor chip 20, the bonding wires 25 and the second BGA substrate 22. Therein, the top surface of the second BGA substrate 22 is exposed from the encapsulant 23 such that packages 26 can be mounted on the second BGA substrate 22.
However, to form the above stacked semiconductor package structure, a reflow process is performed to electrically connect the second BGA substrate 22 to the first BGA substrate 21 through solder balls 24 after the semiconductor chip 20 is electrically connected to the first BGA substrate 21 through bonding wires 25, which not only adversely affects quality of the bonding wires 25, but also brings about contamination of the semiconductor chip 20 and the first BGA substrate 21, thereby reducing product yield and product reliability.
To overcome the above defects, U.S. Pat. No. 6,861,288 proposes a method for fabricating a stacked package semiconductor without performing a reflow process, and the method is illustrated with FIGS. 3A through 3C. First, a semiconductor chip 30 is mounted on a substrate 31, and a metallic stiffener 37 is disposed on the substrate 31 with the semiconductor chip 30 received below the metallic stiffener 37. A stacked substrate 32 is mounted on the metallic stiffener 37, and electrically connected to the substrate 31 through bonding wires 352 (as shown in FIG. 3A). Then, a special mold 38 having an upper mold 381 is disposed on the substrate 31. Therein, the upper mold 381 includes a receiving space 383 and a protruding portion 382 surrounded by the receiving space 383. The receiving space 383 receives the semiconductor chip 30, the stiffener 37, the stacked substrate 32, and the bonding wires 352. The protruding portion 382 extends from an inner top surface of the upper mold 381 and abuts against the top surface of the stacked substrate 32. Thereafter, a molding process is performed to form an encapsulant 33 for encapsulating the semiconductor chip 30, the bonding wires 352 and the stacked substrate 32, as shown in FIG. 3B. Finally, the mold 38 is removed, and a package 36 is mounted on the top surface of the stacked substrate 32 exposed out of the encapsulant 33, as shown in FIG. 3C.
However, the process cost increases because of the introduction of the metallic stiffener 37 into the above-described method. Furthermore, the process cost increases also because the process involves using a special mold to prevent the bonding wires 352 on the substrate 32 from touching the mold.
In addition, during the molding process disclosed in U.S. Pat. Nos. 6,828,664 and 6,861,288, an encapsulant is likely to flash over and contaminate the second BGA substrate or the stacked substrate, thereby bringing trouble to subsequent processes such as a deflash process, a package stacking process and an electrical connection process.
Accordingly, there exists a strong need in the art for a stacked semiconductor structure and fabrication method thereof which can overcome the above defects.